Recent years have seen increasingly higher performance in electronic devices such as portable information devices and information appliances following the development of digital technology. As such, there is an increased demand for larger capacity, reduced writing power consumption, higher speed during writing and reading, and extended operational life in nonvolatile semiconductor memory devices.
In view of these demands, there has been an advance in the miniaturization of flash memories using existing floating gates.
On the other hand, in the case of a nonvolatile semiconductor memory element (variable resistance memory) which uses, in a memory unit, a variable resistance element in which a stably held resistance value changes according to a voltage pulse, a memory cell can be configured using a simple structure, and thus further miniaturization, increase in speed, and reduction of power consumption are expected.
Conventionally, a memory cell that performs stable memory operations is configured using one transistor and one memory element, and increased integration is carried out using this memory cell.
For example, PTL 1 discloses a structure of what is called an 1T1R memory cell in which one memory cell is a combination of one transistor and one variable resistance element, and in which the variable resistance element is configured by forming a variable resistance region in part of a variable resistance layer which is formed directly below an upper electrode and uses a material having a perovskite structure. In PTL 1, the surface area of the lower electrode of the variable resistance element that is in contact with the variable resistance layer and the surface area of the upper electrode that is in contact with the variable resistance layer are different, and the variable resistance region is formed directly above the lower electrode which has a small surface area. Therefore, miniaturization and power consumption reduction can be carried out, since resistance change can be reliably obtained in the vicinity of the electrode having a small connection size, through the application of a current that is smaller than what is conventional.
Furthermore, PTL 2 discloses an example which uses, as a material of the variable resistance element, a material other than the material having the perovskite structure (see FIG. 1 and FIG. 2 of PTL 2). In PTL 2, by using a ferrioxide as a variable resistance layer, the temperature required for manufacturing the variable resistance element can be set to 400° C. or lower, and the compatibility with the semiconductor manufacturing process is improved.